2nd International Workshop on Resistive RAM
October 8 – 9, 2012
Dear Colleague, July 10, 2012
mec and Stanford NMTRI* are jointly organizing
the 2nd International Workshop on Resistive RAM, addressing all
aspects of RRAM (including oxide-based RRAM, CBRAM, selector, and array
considerations). This year, the workshop will be held at the campus of Stanford
University, California, USA, on October 8th and 9th (Monday and Tuesday), 2012.
Resistive memories
are seen today as one of the most promising emerging candidates to become a key
memory technology of the future, with many potential applications, ranging from
replacement of current mass production commodity memories to embedded
applications and even creating novel market segments.
The intention is for
this workshop to serve as a forum gathering key scientists and technologists
working on RRAM, including academia as well as industry, to discuss both the
fundamental mechanisms controlling the operation, scalability and reliability
as well as technological potential and challenges of these exciting
memories.
The 1st International Workshop on Resistive RAM held in October 2011 at IMEC was very successful, with over 160 participants from industry, academia, and research consortia. The program of the previous workshop can be found at:
http://www.imec.be/tcmwebapp/internet/course.tcm?L=EN_GB&K=MTC&Course=AAAAIYE
This year, the
workshop will follow the same successful format of last year. The workshop will
consist of invited talks and panel discussions, as well as a poster session
aimed at encouraging a wider participation including students. To foster
discussions, the workshop will be kept small and participation will be by
invitation only.
On behalf of the Organizing Committee of
the 2nd International Workshop on Resistive RAM, we herewith are pleased to invite you to mark your calendar and
plan on attending this invitation-only workshop. The list of invited speakers
and a draft program is appended below.
Information about the workshop will be
updated on this website:
http://nmtri.stanford.edu/RRAM2012/index.html
We are looking forward to your
participation in this year’s workshop.
Sincerely Yours,
Dr. Dirk Wouters Prof. H.-S. P. Wong Prof. Y.
Nishi Prof. H. Maes
Imec Stanford University Stanford University Sr. VP Imec
Principal Scientist, Professor, Professor, Coordinator CALIT
Memory Electrical Engineering Electrical Engineering
wouters@imec.be hspwong@stanford.edu nishiy@stanford.edu maesh@imec.be
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The event is organized with the
support of Imec’s Center of Advanced Learning in
Information Technologies (CALIT). CALIT is an initiative of IMEC, started in
2004 and that aims at providing a platform for high-level Training Programs
and Events that are visionary and interdisciplinary in nature. CALIT focuses
on a number of themes of high importance and in which cross-disciplinarity is key. Since its start in 2004, 14 CALIT
Visionary Symposia have been organized involving 85 lecturers and attracting
more than 1,650 participants. In addition to these symposia, also brainstorm
sessions, seminars and summer schools have been held for a total of 38
events.
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*Stanford NMTRI (Nonvolatile Memory Technology Research
Initiative) is an industrial affiliate program at Stanford. URL: http://nmtri.stanford.edu/
